Browsing by Author "Corsonello, Pasquale"

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Background subtraction for moving object detection
(2017-02-13) Guachi Guachi, Lorena De Los Angeles; Pantano, Pietro; Cocorullo, Giuseppe; Perri, Stefania; Corsonello, Pasquale
Background Subtraction è una tecnica che si occupa di separare dei cornice di ingresso in significativi oggetti in movimento (foreground) con i rispettivi confini dei (background) oggetti statici che rimangono quiescente per un lungo periodo di tempo per ulteriori analisi. Questo lavora principalmente con telecamere fisse focalizzati sul migliorare la qualità della raccolta di dati al fine di "comprendere le immagini". Questa tecnica per il rilevamento di oggetti in movimento ha diffuse applicazioni nel sistema di visione artificiale con le moderne tecnologie ad alta velocità, insieme con la progressivamente crescente capacità del computer, che fornisce un’ampia gamma di soluzioni reali ed efficienti per la raccolta di informazioni attraverso l’immagine/video come sequenza di ingresso. Un accurato algoritmo per Background Subtraction deve gestire sfide come jitter fotocamera, automatiche regolazioni della fotocamera, i cambiamenti di illuminazione, il bootstrapping, camuffamento, apertura foreground, gli oggetti che vengono a fermarsi e muoversi di nuovo, background dinamici, ombre, scena con diversi oggetti e notte rumorosa. Questa tesi è focalizzata sullo studio della tecnica di Background Subtraction attraverso una panoramica delle sue applicazioni, le sfide, passi e diversi algoritmi che sono stati trovati in letteratura, al fine di proporre approcci efficaci per Background Subtraction per alto performance su applicazioni in tempo reale. Gli approcci proposti hanno consentito indagini di varie rappresentazioni utilizzati per modellare il background e le tecniche considerate per la regolazione dei cambiamenti ambientali, questo ha fornito capacità di vari combinazioni di colori invarianti per segmentare il foreground e anche per eseguire una valutazione comparativa delle versioni ottimizzate del Gaussian Mixture Model e il multimodale Background Subtraction che sono approcci con alte prestazioni per la segmentazione in tempo reale. Deep Learning è stato anche studiato attraverso l’uso di architettura auto-encoder per Background Subtraction
Design Methodologies for FPGA-based Deep Learning Accelerators and Their Characterization
(Università della Calabria, 2023) Sestito, Cristian; Fortino, Giancarlo; Perri, Stefania; Corsonello, Pasquale
Deep Neural Networks (DNNs) are widespread in many applications, including computer vision, speech recognition and robotics, thanks to the ability of such models to extract information by building a hierarchical representation of knowledge. Image processing benefits from the latter behavior by using Convolutional Neural Networks (CNNs), which consist of several Convolutional (CONV) layers to extract features from inputs at different levels of abstraction. However, CNNs usually require billions of computations to reach high accuracy levels. In order to sustain such computational load, proper hardware acceleration is needed. Field Programmable Gate Arrays (FPGAs) have been shown as promising candidates, because they are able to achieve high throughput at limited power dissipation. In addition, FPGAs are flexible architectures to accommodate several CNNs’ workloads. While the hardware acceleration of conventional CNN models has been widely investigated, the interest about more sophisticated tasks is still emerging. The latter includes CNNs based on Dilated Convolutions (DCONVs) and Transposed Convolutions (TCONVs), which deal with filter and image dilations, respectively. Accordingly, higher computational complexity is exhibited by these architectures, thus requiring careful hardware management. This PhD dissertation deals with the FPGA acceleration of CNNs for Image Processing based on DCONVs and TCONVs. Specifically, several designs using both the Very High-Speed Integrated Circuits Hardware Description Language (VHDL) and the High-Level Synthesis (HLS) are presented. Detailed characterization is discussed, based on the evaluation of resources occupation, throughput, power dissipation, as well as the impact of data quantization. Overall, the proposed circuits show noticeable energyefficiency when compared to several state-of-the-art counterparts. For instance, hardware acceleration of run-time reconfigurable CONVs and TCONVs for super-resolution imaging has shown an energy-efficiency of up to 518.5 GOPS/W, by outperforming stateof- the-art competitors by up to 2.3 times.
Heterogeneous FPGA-based Embedded Systems for Vision IoT Applications
(Università della Calabria, 2020-04-23) Spagnolo, Fanny; Crupi, Felice; Perri, Stefania; Corsonello, Pasquale
Embedded sensor devices provided by processing capabilities are opening novel and exciting opportunities in the era of edge-computing Internet-of-Things (IoT). The workload decentralization leads to a plenty of benefits, including better reactivity and reliability and reduced data transfer costs. These advantages have a strong impact especially in the visual IoT field, for which the large bandwidth required by visual data is one of the most critical challenges. However, bringing vision technologies into smart nodes is not a trivial task, because of the stringent energy and performance requirements, in addition to the need of cost-effective and compact processing units. Heterogeneous architectures may represent the key to address these necessities. Among possible heterogeneous platforms, those based on reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) show a high adaptability to a variety of workloads, which is an important goal for edge-computing. Therefore, their deployment in disparate IoT applications, ranging from video surveillance to autonomous driving, is emerging as a promising solution. This dissertation proposes a study on the suitability of modern heterogeneous FPGA System-on-Chips (SoCs) to implement embedded smart vision sensor nodes. To this purpose, several computer vision algorithms aimed to extract synthetic data from raw input frames have been analysed, and novel hardware-oriented solutions have been proposed to deploy them on heterogeneous SoCs. In all the presented cases, ranging from stereo vision to connected component analysis and deep learning, speed performances and/or energy efficiency are considerably improved with respect to state-of-the-art solutions. As an example, the proposed heterogeneous architecture for convolutional neural networks achieves a power efficiency up to 89.5% higher than competitive prior works, demonstrating its suitability in the scenario of energy-constrained and real-time IoT.